The present invention relates generally to reset commands in electronic devices. More particularly, the present invention relates to blocking transactions within a computer system while computer system components are in reset.
In a typical computer system, a reset command may be issued or asserted by a component or device within the computer system. The reset command may instruct all of the components and devices within the computer system to reset to a state of initial conditions or an initial configuration. A component or device of a computer system receiving a reset command or in the process of executing a reset command may be said to be in reset or in a reset condition. A component or device of a computer system that is no longer receiving a reset command or has executed a reset command may be said to be out of reset.
Because a computer system""s processor(s) may be clocked at the highest clock frequency within the computer system, the processor(s) may execute a reset command and be out of reset before other computer system components or devices clocked at relatively lower clock frequencies have executed the reset command. In such cases, a processor or other requesting agent may attempt to issue a transaction on the primary or host bus to a component or device (the xe2x80x9caddressed agentxe2x80x9d or xe2x80x9ctarget agentxe2x80x9d) that is still in reset. In some cases, because the target agent is still in reset, the processor may receive erroneous information from the target agent. In other cases, the processor may erroneously re-boot the entire computer system. Thus, in general, it is desirable that a processor or other requesting agent be prevented or blocked from issuing a transaction on the host bus to a target agent while the target agent is in reset.
There are a variety of schemes in the art for accomplishing this goal. In some situations, the minimum frequency at which target agents may be clocked is limited. In these situations, the minimum clock frequency of the target agents may be limited such that the target agents execute the reset command (and are therefore out of reset) before the processor can itself execute the reset command and issue a transaction to the target agent on the host bus.
There are several disadvantages to this scheme. First, the limit on the minimum clock frequency of the target agent may limit the types of target agents that may be integrated into the computer system. Second, when troubleshooting or debugging a computer system, it may be desirable to clock a target agent at a substantially lower than normal clock frequency, in order to determine whether timing is a cause of the trouble. Clocking a target agent at a substantially lower than normal clock frequency may also enhance signal resolution in display test equipment. Thus, limiting the minimum clock frequency of the target agent may eliminate some methods for debugging computer systems.
In other situations, delay timers for holding the processor(s) in reset have been used. In these situations, the delay timers may be programmed or configured to hold the processor(s) in reset for a certain time period such that the processor(s) are unable to initiate transactions on the host bus before the target agent is out of reset. This scheme also suffers from disadvantages. For example, during some operations, a target agent may be clocked at a normal, relatively high frequency, while during other operations (such as the debugging procedure referenced above), the target agent may be clocked at a relatively low frequency. In such cases, the delay timer, not being responsive to the clock frequency of the target agent, must be programmed or configured to account for the lowest frequency at which the target agent may be clocked (i.e., to account for the longest time period during which the target agent may be in reset). Thus, in situations where the target agent is seldom clocked at the relatively low frequency, the delay timer scheme will, more often than not, hold the processor in reset for a longer time period than is necessary for the target agent to be out of reset and accessible over the host bus. Thus, the delay timer may unnecessarily prolong, for example, the computer system""s boot-up process.
In still other situations, both of the above schemes have be jointly implemented. While this may help to alleviate the magnitude of the disadvantages discussed above, the disadvantages themselves will remain.
Thus, there exists a need in the art for improved apparatus and methods for controlling the transactions on a host bus to prevent the host from accessing a target agent while the target agent is in reset.
The present invention comprises a host bus clocked in a host clock domain, a secondary bus for receiving a reset command clocked in a secondary bus clock domain and a controller for dynamically delaying transactions on the host bus until the secondary bus is out of reset.